Reconfigurable processors process information via normal (von Neumann) processors used with highly flexible computing fabrics often made of field-programmable gate arrays, FPGAs. Normal processors can reconfigure (make changes to) software (programs, control flow), but not hardware (data paths). Reconfigurable processors can reconfigure control flow, and data paths. Reconfiguration can occur during deployment, between execution phases, or during execution. In typical reconfigurable systems, a bit stream is used to program devices during deployment. These often achieve a 10-100 fold increase in computing density and speed (reduced latency) over normal processors.
Subcategories 3
Related categories 2
Sites 9
Berkeley Reconfigurable Architectures, Systems, and Software
Researches many system-level technologies, focusing on integrating processors and reconfigurable logic.
HThreads
Hybridthreads, efficient hardware accelerated computating platform: operating system runs on hybrid CPU/FPGA chip, 2 sets of APIs give access to OS; platform has high level language compiler, can compile C source code into hardware components. University of Kansas.
NASA Office of Logic Design
Researches and funds many aspects of design and use of programmable and quick-turn technologies, for space flight uses.
RAMP: Research Accelerator for Multiple Processors
FPGA-based multiprocessor functional simulator framework. University of California, Berkeley.
Research
Summary of topic, with some uses, at University of Wisconsin, Madison.
Virginia Tech Configurable Computing Laboratory
Research many aspects of dynamic computing, electronic and computing fabrics, soft processor arrays.
Wikipedia: Reconfigurable Computing
Encyclopedia article, with links to many related topics.
Xputer Lab Configware Engineering for Reconfigurable Computing with KressArray
Home of former Computer Structures Group: reconfigurable computing, soft IP core, soft machine, anti machine soft datapath, soft machine paradigm, fpga, KressArray. Kaiserslautern University of Technology, Kaiserslautern, Germany.
Raytheon Develops World's First Polymorphic Computer
MONARCH: Morphable Networked Micro-Architecture; adaptable processor is 10 times faster than Intel Xeon quad-core chip. Military Embedded Systems.
(March 20, 2007)
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July 5, 2016 at 6:35:10 UTC